Conventionally, a SiC single crystal wafer having high quality is disclosed in the patent documents No. 1 and No. 2. The SiC single crystal wafer, disclosed in the patent documents No. 1 and No. 2 is suitably used for processing a device under a condition that a density of dislocations, which negatively affects on device characteristics, is equal to or smaller than a certain value. Here, the dislocation is a crystal defect along with a line. The types of dislocations as an object are a basal plane dislocation disposed on a (0001)-plane face (i.e., C-face) and a threading screw dislocation in parallel to a C-axis.    [Patent document No. 1] JP-A-2008-115034    [Patent document No. 2] JP-A-2008-515748 corresponding to U.S. Pat. No. 7,314,520
However, the patent documents No. 1 and No. 2 do not teach a threading edge dislocation, and thereby, influence of the threading edge dislocation on the device is not clear. Thus, the threading screw dislocation and the threading edge dislocation (both are defined as threading dislocation) cause device characteristics of a diode and a transistor to be deteriorated, and/or reduce manufacturing yield ratio. Thus, it is important to reduce the density of dislocations. Although the patent documents No. 1 and No. 2 teaches the types of dislocations and density thereof, a direction of a dislocation line of a threading dislocation is not clear.
Here, the threading screw dislocation and the threading edge dislocation have different directions of distortion (i.e., different Burgers vectors). The direction of distortion in the threading screw dislocation is in parallel to the C-axis, and the direction of distortion in the threading edge dislocation is perpendicular to the C-axis. The direction of distortion in a basal plane dislocation includes both of the directions of dislocation in the screw dislocation and the edge dislocation.